2. The Field of the Invention
The present invention relates to the fabrication of integrated circuits. More particularly, the present invention relates to an anti-reflective enhancement for integrated circuit fabrication. In particular, the present invention relates to an anti-reflective enhancement for reducing critical dimension loss during mask patterning.
3. The Relevant Technology
In the microelectronics industry, a substrate refers to one or more semiconductor layers or structures which includes active or operable portions of semiconductor devices. In the context of this document, the term "semiconductive substrate" is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term substrate refers to any supporting structure including but not limited to the semiconductive substrates described above.
In the microelectronics industry, the process of miniaturization entails shrinking the size of individual semiconductor devices and crowding more semiconductor devices within a given unit area. With miniaturization, problems arise with proper electrical isolation between components. When miniaturization demands the shrinking of individual devices, isolation structures must also be shrunk. Attempts to isolate components from each other in the prior art are limited to photolithographic limits of about 0.25 microns. One way to form structures that electrically isolate conductive materials on a semiconductor substrate from each other is to use photolithography in patterning dielectrics layers upon the semiconductor substrate.
To form an isolation trench on a semiconductor substrate by photolithography, a photoresist mask through which the isolation trench is etched generally utilizes a beam of light, such as ultraviolet (UV) light and deep UV (DUV) light, to transfer a pattern through an imaging lens from a photolithographic template to a photoresist coating which has been applied to the structural layer being patterned. The pattern of the piotolithographic templat includes opaque and transparent regions with selected shapes that match corresponding openings and intact portions intended to be formed into the photoresist coating. The photolithographic template is conventionally designed by computer assisted drafting and is of a much larger size than the semiconductor wafer on which the photoresist coating is located. Light is directed through the photolithographic template and is focused on the photoresist coating in a manner that reduces the pattern of the photolithographic template to the size of the photolithographic coating and that develops the portions of the photoresist coating that are unmasked and are intended to remain. The undeveloped portions are thereafter easily removed. Other photolithographic techniques for formation of isolation trenches are also possible.
The resolution with which a pattern can be transferred the photoresist coating from the photolithographic template is currently limited in commercial applications to widths of about 0.25 microns. In turn, the dimensions of the openings and intact regions of the photoresist mask, and consequently the dimensions of the shaped structures that are formed with the use of the photoresist mask, are correspondingly limited. Photolithographic resolution limits are thus a barrier to further miniaturization of integrated circuits. Accordingly, a need exists for an improved method of forming isolation trenches that have a size that is reduced from what can be formed with conventional photolithography.
During photolithography, reflected light that occurs during exposure of a mask tends to blur the desired image because the reflected light escapes beyond exposed regions on the photoresist. The blurring problem is caused by reflected light affecting areas of the photoresist that are outside the design pattern.
FIG. 1 illustrates the problem of blurring caused by reflected light that occurs during exposure of a photoresist. A semiconductor structure 10 may be, for example, an isolated active area 8X that was designed to have a width D, but due to blurring caused by reflectivity of patterning light from structures beneath the photorcsist, isolated active area 8X has an actual width A. The variance between design width D and actual width A is illustrated as the distance 2(B/2) or B. By way of example, isolated active area 8X was designed to have a width D of 10 in arbitrary units, but due to blurring caused from reflectivity, the actual width A is nine in arbitrary units. It can be seen that a ten percent variance between design and actual width has occurred.
As miniaturization technology continues, a blurring variance of B as illustrated in FIG. 1 will increase relative to an ever-decreasing design width D. Thus, as also illustrated in FIG. 1, an isolated active area 8Z that may have a design width D' of, for example two and one-half in arbitrary units, variance B will have the effect of causing a 40 percent error. A variance B may leave insufficient space upon isolated active area 8Z to form desired contacts or structures. It can be seen from the demonstration illustrated in FIG. 1, that the need to eliminate or substantially reduce blurring must keep pace with miniaturization.
Prior art methods for avoiding reflected light and its photoresist blurring problems include using layers such as titanium nitride or organic materials that reduce the reflected light in order to better control resolution of the photoresist.
Another hindrance to photolithographic limitations are conventional antireflective coating (ARC) schemes. As the ever-increasing pressure to miniaturize bears upon the microelectronics industry, the conventional antireflective enhancements such as a titanium nitride layer, organic layers, or other layers known in the art are proving inadequate at resolutions below about 0.25 microns.
One problem at a dimension below about 0.25 microns is that of fouling caused by titanium nitride or organic materials. Fouling is defined as a tendency for a selected antireflective layer to resist staying within preferred boundaries. Resistance to staying within preferred boundaries tends to cause photolithographic techniques to be compromised.
When the ARC is a polymer film, it is applied directly to the semiconductor structure to a thickness of about 0.5 microns and photoresist is deposited on top of the ARC. The ARC then has the function of absorbing most of the radiation used during exposure of the resist that penetrates the resist material. Both standing wave effects and destructive scattering from typographical features are suppressed with use of the ARC. A disadvantage of a polymer film ARC is that the process is increased in complexity and dimensional control may be lost. A polymer film ARC requires application by spin coating of the ARC material and pre-baking of same before applying the photoresist material. A problem of removing the ARC exists following an etch. For example, during anisotropic etching, portions of a photoresist are mobilized and form a liner within a recess that is being etched that further assists in achieving the anisotropic etch. Due to the anisotropic etch, however, the photoresist that was mobilized may have mingled with other elements that cause it to resist removal by conventional stripping techniques. This resistance to stripping requires stripping solutions that have a chemical intensity that may detrimentally effect the structure that was achieved during the anisotropic etch. Thus, using a substance that is intended to aid anti-reflectivity the benefit thereof mitigated by the requirement of a more chemically intensive stripping solution treatment.
Another method of attempting to avoid reflected light is to use a metallic mask. Metallic materials, however, can cause contamination of the semiconductor structure due to the high mobility of metal ions in wet chemical environments or in dry-etch vapors. Additionally, although a metallic mask may remain as part of a finished semiconductor structure, a metallic mask may not be able to properly withstand high processing temperatures sometimes required to achieve a preferred semiconductor structure.
One application in the microelectronics industry is to isolate active areas by substantially surrounding them with dielectric structures. As dimensions shrink below about 0.25 microns, the prior art technique of growing a local oxidation of silicon (LOCOS) to isolate an active area becomes more difficult to achieve. This difficulty is due to the inability to control encroachment of the LOCOS structure into the active area during growth of the LOCOS. Several techniques have been developed to control the encroachment of what is called the "bird's beak" of the LOCOS into the active area, but these techniques require extra operations, each of which adds to fabrication time and cost as well as tending to lower overall fabrication yield.
Alternatively, isolated active areas have been fabricated by forming trenches on either side of a semiconductor region and by depositing dielectric materials into the trenches. The challenge for isolation trenches that isolate an active area with a width of less than about 0.25 microns is in overcoming the inherent problems of reflected light and antireflective coatings of the prior art as discussed above. Light that is reflected during exposure of a photoresist tends to blur the boundary between the active area and the trench such that the trench that is eventually etched encroaches into a designed active area and the designed active area is dimensionally compromised or rendered defective.
In general, several problems are caused by reflected light in photolithographic techniques which blur the edge of a critically dimensioned photoresist layer. In addition to problems experienced in forming isolation trenches, contact corridors, vias, and wiring trenches that must be patterned below about 0.25 microns are also blurred and are therefore widened beyond that which is preferred. A contact corridor that is too wide will cause notching into a gate stack during a contact corridor etch. Notching causes encroachment into conductive areas of a gate stack and filling the contact corridor with metallization causes a short to occur between the contact and the conductive elements of the gate stack. A trench that is too wide will cause "cross talk" between neighboring trenches so as so to compromise speed and accuracy of the integrated circuit associated therewith.
What is needed is an antireflective coating scheme that does not substantially add to fabrication cost and does not substantially reduce fabrication yield. What is also needed is an antireflective coating scheme that imparts an antireflective quality to photolithographic techniques not previously achieved in the prior art. What is also needed is an antireflective coating scheme that does not cause fouling of the semiconductor structure. Additionally, what is needed is an antireflective coating scheme that either does not require removal, or that can be removed without causing contamination or damage to the semiconductor structure. What is also needed is an antireflective coating scheme that facilitates a better photoresist profile and better control of critical dimensions due to better prevention of reflected light than is found in the prior art.